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from the manual:
One of the unique features of the Intel 432 is its instruction
encoding. Instructions are bit-variable in length and can start
on any bit boundary. The instruction pointer thus contains the
bit offset into the current instruction segment, which can be up
to 8K bytes in size. An instruction consists of up to four fields,
as shown in Figure 9-14. The fields themselves are also variable-length and highly encoded
but bit-addressable instructions isn't something you see very often! i think i've only seen a few microcontrollers that support this, like the sm83. there, bit-addressable memory is only for a range of memory, with byte addressing for the rest of memory. and instructions were all pretty fixed size
bit-granularity instruction sizes is also *extremely* weird and the thing everyone gets weirded out with about the 432. personally the interesting question is what was intel optimizing for? or, who designed the isa? presumably hardware folks believed it wouldn't be too cumbersome to implement. instructions with variable bit widths of almost all items though, wow. they really should put credits in the manual to see what else these people get up to. maybe some of them ended up on ia64, where there's some other instruction encoding cleverness kinda like this?
and anyway this suggests they were really concerned about maximally packing instruction encoding space. x86 isn't so great at this, and if you look at arm you can see how this pans out when you want an extensible but fixed-size instruction. kinda wild encodings over there. so with this your encodings look more like a huffman tree when you assume the most common instructions are the first ones you spec out. adds, copies, compares, that kinda stuff.
i really gotta find some 432 programs and write a disassembler. maybe i can con someone into writing a softcore for one of these and we can run some 1980s era code...
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